View MAX17101_4677544.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator ________________________________________________________________ maxim integrated products 1 ordering information 19-4243; rev 1; 2/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the MAX17101 is a dual quick-pwm? step-down power-supply (smps) controller with synchronous rectifi- cation, intended for main 5v/3.3v power generation in battery-powered systems. low-side mosfet sensing provides a simple low-cost, highly efficient current sense for providing valley current-limit protection. combined with the output overvoltage and undervoltage protection features, this current limit ensures robust output supplies. the 5v/3.3v smps outputs can save power by operating in pulse-skipping mode or in ultrasonic mode to avoid audible noise. ultrasonic mode forces the controller to maintain switching frequencies greater than 20khz at light loads. an internal 100ma linear regulator can be used to either generate the 5v bias needed for power-up or other lower power always-on suspend supplies. an independent bypass input allows automatic bypassing of the linear regulator when the smps is active. this main controller also includes a secondary feed- back input that triggers an ultrasonic pulse (dl1 turned on) if the secfb voltage drops below its threshold volt- age. this refreshes an external charge pump driven by dl1 without overcharging the output voltage. the device includes independent shutdown controls to simplify power-up and power-down sequencing. to prevent current surges at startup, the internal voltage target is slowly ramped up from zero to the final target over a 1ms period. to prevent the output from ringing below ground in shutdown, the internal voltage target is ramped down from its previous value to zero over a 1ms period. two independent power-good outputs simplify the interface with external controllers. the MAX17101 comes in a lead-free 32-pin tqfn (5mm x 5mm) package and operates in the -40c to +85c temperature range. features applications + denotes a lead-free/rohs-compliant package. * ep = exposed pad. part temp range pin-package MAX17101etj+ -40c to +85c 32 thin qfn-ep* dual quick-pwm internal 100ma 5v or adjustable linear regulator independent ldo bypass input internal boost diodes secondary feedback input maintains charge pump 3.3v 5ma rtc power (always on) out1: 5v or 1.5v fixed or 0.7v adjustable feedback out2: 3.3v or 1.05v fixed or dynamic adjustable dynamic 0 to 2v refin2 input on second output 2v ?% 50? reference 6v to 24v input range (28v max) ultrasonic mode independent smps and ldo enable controls independent smps power-good outputs minimal component count notebook computers main system supply (5v and 3.3v supplies) graphic cards ddr1, ddr2, ddr3 power supplies game consoles low-power i/o and chipset supplies two to four li+ cells battery-powered devices pdas and mobile communicators telecommunication MAX17101 thin qfn top view a "+" sign first-pin indicator denotes a lead-free package. 29 30 28 27 12 11 13 ton onldo rtc in ldo 14 ref dl2 agnd secfb bst2 v dd dl1 12 pgood2 4567 23 24 22 20 19 18 skip out2 on1 pgood1 ilim1 fb1 v cc pgnd 3 21 31 10 ilim2 out1 32 9 refin2 + byp on2 26 15 dh1 dh2 25 16 lx1 ldosel bst1 8 17 lx2 pin configuration quick-pwm is a trademark of maxim integrated products, inc. evaluation kit available
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1, no load on ldo, rtc, out1, out2, and ref, v in = 12v, v dd = v cc = v secfb = 5v, v refin2 = 1.0v, byp = ldosel = gnd, onldo = in, on1 = on2 = v cc , t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, onldo to gnd ................................................-0.3v to +28v v dd , v cc to gnd .....................................................-0.3v to +6v rtc, ldo to gnd ....................................................-0.3v to +6v out_ to gnd ...........................................................-0.3v to +6v on1, on2 to gnd....................................................-0.3v to +6v pgood_ to gnd........................................-0.3v to (v cc + 0.3v) ref, ilim_, ton, skip to gnd ..................-0.3v to (v cc + 0.3v) fb1, refin2, ldosel to gnd ................................-0.3v to +6v secfb to gnd .........................................................-0.3v to +6v byp to gnd..............................................-0.3v to (v ldo + 0.3v) gnd to pgnd .......................................................-0.3v to +0.3v dl_ to pgnd ..............................................-0.3v to (v dd + 0.3v) bst_ to gnd ..........................................................-0.3v to +34v bst_ to v dd ............................................................-0.3v to +28v dh1 to lx1 ..............................................-0.3v to (v bst1 + 0.3v) bst1 to lx1..............................................................-0.3v to +6v dh2 to lx2 ..............................................-0.3v to (v bst2 + 0.3v) bst2 to lx2..............................................................-0.3v to +6v ldo, rtc, ref short circuit to gnd.........................momentary rtc current continuous.....................................................+5ma ldo current (internal regulator) continuous..................................................................+100ma ldo current (switched over) continuous .....................+200ma continuous power dissipation (t a = +70c) 32-pin 5mm x 5mm tqfn (derate 34.5mw/c above +70c) .................................2.76w operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c parameter symbol conditions min typ max units input supplies in standby supply current i in(stby) v in = 6v to 24v, on1 = on2 = gnd, onldo = v cc 85 175 a in shutdown supply current i in(shdn) v in = 4.5v to 24v, on1 = on2 = onldo = gnd 50 70 a in supply current i in on1 = on2 = refin2 = v cc , skip = fb1 = gnd, v out2 = 3.5v, v out1 = 5.3v 0.1 0.2 ma v cc supply current i cc on1 = on2 = refin2 = v cc , skip = fb1 = gnd, v out2 = 3.5v, v out1 = 5.3v 1.0 1.5 ma pwm controllers 5v preset output: fb1 = gnd, v in = 12v, skip = v cc 4.925 5.00 5.075 v out1 1.5v preset output: fb1 = v cc (5v), v in = 12v, skip = v cc 1.482 1.50 1.518 out1 output-voltage accuracy (note 1) v fb1 adjustable feedback output, v in = 12v, skip = v cc 0.690 0.700 0.710 v out1 voltage-adjust range 0.7 5.5 v low 0.04 0.110 fb1 dual mode? threshold voltage levels high v cc - 1.6v v cc - 0.7v v fb1 input bias current i fb1 v fb1 = 0.8v, t a = +25c -0.2 +0.2 a dual mode is a trademark of maxim integrated products, inc.
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, no load on ldo, rtc, out1, out2, and ref, v in = 12v, v dd = v cc = v secfb = 5v, v refin2 = 1.0v, byp = ldosel = gnd, onldo = in, on1 = on2 = v cc , t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units 3.3v preset output: refin2 = v cc (5v), v in = 12v, skip = v cc 3.255 3.30 3.345 1.05v preset output: refin2 = rtc (3.3v), v in = 12v, skip = v cc 1.038 1.050 1.062 out2 output-voltage accuracy (note 1) v out2 tracking output: v refin2 = 1.1v, v in = 12v, skip = v cc 1.09 1.10 1.11 v out2 voltage-adjust range 0.8 2.0 v refin2 voltage-adjust range 0 2 v v refin2 = 2.2v, t a = +25c -0.1 +0.1 refin2 input bias current i refin2 v refin2 = 0v, t a = +25c -0.5 +0.1 a low (refin2 = rtc) 2.2 3.0 refin2 dual mode threshold voltage levels high (refin2 = v cc ) v cc - 1.0v v cc - 0.4v v either smps, skip = v cc , i load = 0 to 5a -0.1 either smps, skip = ref, i load = 0 to 5a -1.7 load regulation error either smps, skip = gnd, i load = 0 to 5a -1.5 % line regulation error either smps, v in = 6v to 24v 0.005 %/v ton = gnd or ref (400khz) 895 1052 1209 dh1 on-time t on1 v in = 12v, v out1 = 5.0v (note 2) ton = v cc (200khz) 2105 ns ton = gnd (500khz) 555 dh2 on-time t on2 v in = 12v, v out2 = 3.3v (note 2) ton = ref or v cc (300khz) 833 925 1017 ns minimum off-time t off(min) (note 2) 300 400 ns soft-start/stop slew rate t ss rising/falling edge on on1 or on2 (preset) 1 ms soft-start/stop slew rate t ss rising/falling edge on on2 (refin2 adj) 1 mv/s dynamic refin2 slew rate t dyn rising edge on refin2 8 mv/s ultrasonic operating frequency f sw(usonic) skip = open (ref) 20 27 khz secfb threshold voltage v secfb 1.94 2.0 2.06 v secfb input bias current i secfb v secfb = 2.2v, t a = +25c -0.2 +0.2 a linear regulator (ldo) v in = 24v, ldosel = byp = gnd, 0 < i ldo < 100ma 4.90 5.0 5.10 ldo output-voltage accuracy v ldo v in = 24v, ldosel = v cc , byp = gnd, 0 < i ldo < 100ma 3.23 3.3 3.37 v ldosel low 0.1 0.15 0.2 ldosel dual mode threshold voltage levels ldosel high v cc - 0.9v v
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, no load on ldo, rtc, out1, out2, and ref, v in = 12v, v dd = v cc = v secfb = 5v, v refin2 = 1.0v, byp = ldosel = gnd, onldo = in, on1 = on2 = v cc , t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units ldo short-circuit current i ilim(ldo) ldo = gnd 100 260 ma ldo regulation reduction/ bypass switchover threshold with respect to the ldo voltage, falling edge of byp -11.0 -8.5 -6.0 % ldo bypass switchover threshold with respect to the ldo voltage, rising edge of byp -6.5 % ldo bypass switchover startup timeout t byp rising edge of byp to bypass gate pulled low 500 s ldo bypass switch resistance ldo to byp, v byp = 5v (note 4) 1.2 4.5 falling edge of v cc , pwm disabled below this threshold 3.8 4.0 4.3 v cc undervoltage-lockout (uvlo) threshold v uvlo(vcc) rising edge of v cc 4.2 v thermal-shutdown threshold t shdn hysteresis = 10c +160 c 3.3v always-on linear regulator (rtc) on1 = on2 = gnd, v in = 6v to 24v, 0 < i rtc < 5ma 3.23 3.33 3.43 rtc output-voltage accuracy v rtc on1 = on2 = onldo = gnd, v in = 6v to 24v, 0 < i rtc < 5ma 3.16 3.50 v rtc short-circuit current i ilim(rtc) rtc = gnd 5 ma reference (ref) reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.980 2.00 2.020 v reference load regulation v ref i ref = -20a to +50a -10 +10 mv ref lockout voltage v ref(uvlo) rising edge, 350mv (typ) hysteresis 1.95 v out1 fault detection out1 overvoltage trip threshold v ovp(out1) with respect to error-comparator threshold 12 16 20 % out1 overvoltage fault-propagation delay t ovp fb1 forced 50mv above trip threshold 10 s out1 undervoltage protection trip threshold v uvp(out1) with respect to error-comparator threshold 65 70 75 % out1 output-undervoltage fault-propagation delay t uvp 10 s pgood1 lower trip threshold with respect to error-comparator threshold, falling edge, hysteresis = 1% -20 -16 -12 % pgood1 propagation dela y t pgood1 fb1 forced 50mv beyond pgood1 trip threshold, falling edge 10 s pgood1 output low voltage v fb1 = 0.56v (pgood1 low impedance), i sink = 4ma 0.3 v pgood1 leakage current i pgood1 v fb1 = 0.70v (pgood1 high impedance), pgood1 forced to 5.5v 1 a
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1, no load on ldo, rtc, out1, out2, and ref, v in = 12v, v dd = v cc = v secfb = 5v, v refin2 = 1.0v, byp = ldosel = gnd, onldo = in, on1 = on2 = v cc , t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units out2 fault detection with respect to error-comparator threshold 12 16 20 % out2 overvoltage trip threshold v ovp(out2) minimum overvoltage threshold 0.7 v out2 overvoltage fault-propagation delay t ovp out2 forced 50mv above trip threshold 10 s out2 undervoltage protection trip threshold v uvp(out2) with respect to error-comparator threshold 65 70 75 % out2 overvoltage fault-propagation delay t ovp out2 forced 50mv above trip threshold 10 s out2 output undervoltage fault-propagation delay t uvp out2 forced 50mv below trip threshold 10 s pgood2 lower trip threshold with respect to error-comparator threshold, falling edge, hysteresis = 2% -20 -16 -12 % pgood2 propagation dela y t pgood2 out2 forced 50mv beyond pgood1 trip threshold, falling edge 10 s pgood2 output-low voltage v out2 = v refin2 - 150mv (pgood2 low impedance), i sink = 4ma 0.3 v pgood2 leakage current i pgood2 out2 = refin2 (pgood2 high impedance), pgood2 forced to 5.5v, t a = +25c 1 a current limit ilim_ adjustment range v ilim 0.2 2.0 v ilim_ current i ilim 5 a r ilim _ = 100k 40 50 60 valley current-limit threshold (adjustable) v valley v agnd - v lx _ r ilim _ = 200k 87 100 113 mv current-limit threshold (negative) v neg with respect to valley current-limit threshold, skip = v cc -120 % ultrasonic current-limit threshold v neg(us) v out1 = v out2 = v fb1 = 0.77v, v refin2 = 0.70v 25 mv current-limit threshold (zero crossing) v zx v agnd - v lx _, skip = gnd or open/ref 1 mv
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, no load on ldo, rtc, out1, out2, and ref, v in = 12v, v dd = v cc = v secfb = 5v, v refin2 = 1.0v, byp = ldosel = gnd, onldo = in, on1 = on2 = v cc , t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units gate drivers dh_ gate driver on-resistance r dh bst1 - lx1 and bst2 - lx2 forced to 5v 1.5 3.5 dl1, dl2; high state 2.2 4.5 dl_ gate driver on-resistance r dl dl1, dl2; low state 0.6 1.5 dh_ gate driver source/sink current i dh dh1, dh2 forced to 2.5v, bst1 - lx1 and bst2 - lx2 forced to 5v 2 a dl_ gate driver source current i dl (source) dl1, dl2 forced to 2.5v 1.7 a dl_ gate driver sink current i dl (sink) dl1, dl2 forced to 2.5v 3.3 a internal bst_ switch on-resistance r bst i bst _ = 10ma, v dd = 5v 5 inputs and outputs high v cc - 0.4v ref or open 1.6 3.0 ton input logic levels low 0.4 v high (forced pwm) v cc - 0.4v open (ultrasonic) 1.6 3.0 skip input logic levels low ( skip ) 0.4 v skip , ton leakage current i skip , i ton v skip = v ton = 0 or 5v, t a = +25c -2 +2 a high (smps on) 2.4 on_ input logic levels low (smps off) 0.8 v on_ leakage current i on_ v on1 = v on2 = 0 or 5v, t a = +25c -2 +2 a high (smps on) 2.4 onldo input logic levels low (smps off) 0.8 v onldo leakage current i onldo v onldo = 0 or 24v, t a = +25c -1 +1 a
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator _______________________________________________________________________________________ 7 electrical characteristics (circuit of figure 1, no load on ldo, rtc, out1, out2, and ref, v in = 12v, v dd = v cc = v secfb = 5v, v refin2 = 1.0v, byp = ldosel = gnd, onldo = in, on1 = on2 = v cc , t a = -40? to +85? , unless otherwise noted.) (note 3) parameter symbol conditions min typ max units input supplies in standby supply current i in(stby) v in = 6v to 24v, on1 = on2 = gnd, onldo = v cc 200 a in shutdown supply current i in(shdn) v in = 4.5v to 24v, on1 = on2 = onldo = gnd 70 a in supply current i in on1 = on2 = refin2 = v cc , skip = fb1 = gnd, v out2 = 3.5v, v out1 = 5.3v 0.2 ma v cc supply current i cc on1 = on2 = refin2 = v cc , skip = fb1 = gnd, v out2 = 3.5v, v out1 = 5.3v 1.5 ma pwm controllers 5v preset output: fb1 = gnd, v in = 12v, skip = v cc 4.90 5.10 v out1 1.5v preset output: fb1 = v cc (5v), v in = 12v, skip = v cc 1.47 1.53 out1 output-voltage accuracy (note 1) v fb1 adjustable feedback output, v in = 12v, skip = v cc 0.685 0.715 v out1 voltage-adjust range 0.7 5.5 v low 0.040 0.125 fb1 dual mode threshold voltage high v cc - 1.6v v cc - 0.7v v 3.3v preset output: refin2 = v cc (5v), v in = 12v, skip = v cc 3.234 3.366 1.05v preset output: refin2 = rtc (3.3v), v in = 1.2v, skip = v cc 1.029 1.071 out2 output-voltage accuracy (note 1) v out2 tracking output: v refin2 = 1.1v, v in = 12v, skip = v cc 1.085 1.115 v out2 voltage-adjust range 0 2 v refin2 voltage-adjust range 0 2 v low (refin2 = rtc) 2.2 3.0 refin2 dual mode threshold voltage high (refin2 = v cc ) v cc - 1.2v v cc - 0.4v v ton = gnd or ref (400khz) 895 1209 dh1 on-time t on1 v in = 12v, v out1 = 5.0v (note 2) ton = ref or v cc (300khz) 833 1017 ns minimum off-time t off(min) (note 2) 450 ns secfb threshold voltage v secfb 1.92 2.08 v
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 8 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, no load on ldo, rtc, out1, out2, and ref, v in = 12v, v dd = v cc = v secfb = 5v, v refin2 = 1.0v, byp = ldosel = gnd, onldo = in, on1 = on2 = v cc , t a = -40? to +85? , unless otherwise noted.) (note 3) parameter symbol conditions min typ max units linear regulator (ldo) v in = 24v, ldosel = byp = gnd, 0 < i ldo < 100ma 4.85 5.15 ldo output-voltage accuracy v ldo v in = 24v, ldosel = v cc , byp = gnd, 0 < i ldo < 100ma 3.20 3.40 v ldosel low 0.25 ldosel dual mode voltage level ldosel high v cc - 0.9v v ldo short-circuit current i ilim(ldo) ldo = gnd 260 ma ldo regulation reduction/ bypass switchover threshold falling edge of byp -12 -5 % v cc undervoltage-lockout threshold v uvlo(vcc) falling edge of v cc , pwm disabled below this threshold 3.8 4.3 v 3.3v always-on linear regulator (rtc) on1 = on2 = gnd, v in = 6v to 24v, 0 < i rtc < 5ma 3.18 3.45 rtc output-voltage accuracy v rtc on1 = on2 = onldo = gnd, v in = 6v to 24v, 0 < i rtc < 5ma 3.16 3.50 v rtc short-circuit current i ilim(rtc) rtc = gnd 5 ma reference (ref) reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.975 2.025 v reference load-regulation error v ref i ref = -20a to +50a -10 +10 mv out1 fault detection out1 overvoltage trip threshold v ovp(out1) with respect to error-comparator threshold 10 20 % out1 undervoltage-protection trip threshold v uvp(out1) with respect to error-comparator threshold 60 80 % pgood1 lower trip threshold with respect to error-comparator threshold, falling edge, hysteresis = 1% -20 -10 % pgood1 output-low voltage v fb1 = 0.56v (pgood1 low impedance), i sink = 4ma 0.4 v out2 fault detection out2 overvoltage trip threshold v ovp(out2) with respect to error-comparator threshold 10 20 %
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator _______________________________________________________________________________________ 9 electrical characteristics (continued) (circuit of figure 1, no load on ldo, rtc, out1, out2, and ref, v in = 12v, v dd = v cc = v secfb = 5v, v refin2 = 1.0v, byp = ldosel = gnd, onldo = in, on1 = on2 = v cc , t a = -40? to +85? , unless otherwise noted.) (note 3) parameter symbol conditions min typ max units out2 undervoltage-protection trip threshold v uvp(out2) with respect to error-comparator threshold 60 80 % pgood2 lower trip threshold with respect to error-comparator threshold, falling edge, hysteresis = 2% -20 -10 % pgood2 output-low voltage v out2 = v refin2 - 150mv (pgood2 low impedance), i sink = 4ma 0.4 v current limit ilim_ adjustment range v ilim 0.2 2.0 v r ilim _ = 100k 40 60 valley current-limit threshold (adjustable) v valley v agnd - v lx _ r ilim _ = 200k 85 115 mv gate drivers dh_ gate driver on-resistance r dh bst1 - lx1 and bst2 - lx2 forced to 5v 3.5 dl1, dl2; high state 4.5 dl_ gate driver on-resistance r dl dl1, dl2; low state 1.5 inputs and outputs high v cc - 0.4v ref or open 1.6 3.0 ton input logic levels low 0.4 v high (forced pwm) v cc - 0.4v open (ultrasonic) 1.6 3.0 skip input logic levels low (skip) 0.4 v high (smps on) 2.4 on_ input logic levels low (smps off) 0.8 v high (smps on) 2.4 onldo input logic levels low (smps off) 0.8 v note 1: dc output accuracy specifications refer to the threshold of the error comparator. when the inductor is in continuous conduc- tion, the MAX17101 regulates the valley of the output ripple, so the actual dc output voltage is higher than the trip level by 50% of the output ripple voltage. in discontinuous conduction (i out < i load(skip) ), the output voltage has a dc regulation level higher than the error-comparator threshold by approximately 1.5% due to slope compensation. note 2: on-time and off-time specifications are measured from 50% point to 50% point at the dh pin with lx = pgnd, v bst = 5v, and a 500pf capacitor from dh to lx to simulate external mosfet gate capacitance. actual in-circuit times might be differ- ent due to mosfet switching speeds. note 3: specifications to t a = -40c are guaranteed by design and not production tested. note 4: specifications increased by 1 to account for test measurement error.
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 10 ______________________________________________________________________________________ 5v output efficiency vs. load current MAX17101 toc01 load current (a) efficiency (%) 1 0.1 60 55 70 80 90 65 75 85 95 100 50 0.01 10 20v 12v 7v skip mode pwm mode 5v output efficiency vs. load current MAX17101 toc02 load current (a) efficiency (%) 1 0.1 60 70 80 90 100 50 65 75 85 95 55 0.01 10 skip mode pwm mode ultrasonic mode 12v 3.3v output efficiency vs. load current MAX17101 toc03 load current (a) efficiency (%) 1 0.1 60 70 80 90 100 50 65 75 85 95 55 0.01 10 20v 12v 7v 5v smps enabled skip mode pwm mode 3.3v output efficiency vs. load current MAX17101 toc04 load current (a) efficiency (%) 1 0.1 60 70 80 90 100 50 65 75 85 95 55 0.01 10 skip mode 5v smps enabled pwm mode ultrasonic mode 12v smps output voltage deviation vs. load current MAX17101 toc05 load current (a) output voltage deviation (%) 1 0.1 -2 -1 0 1 2 3 -3 0.01 10 pwm mode 12v low-noise ultrasonic skip mode switching frequency vs. load current MAX17101 toc06 load current (a) switching frequency (khz) 1 0.1 10 100 1000 1 0.01 10 pwm mode low-noise ultrasonic mode skip mode 12v 5v ldo output voltage vs. load current MAX17101 toc07 load current (ma) output voltage (v) 100 120 40 60 80 4.9 4.8 5.1 5.0 5.2 4.7 0 20 140 3.3v rtc output voltage vs. load current MAX17101 toc08 load current (ma) output voltage (v) 10 468 3.2 3.1 3.3 3.5 3.4 3.0 02 12 no-load input supply current vs. input voltage MAX17101 toc09 input voltage (v) supply current (ma) 15 20 510 1 10 100 0.01 0.1 025 pwm mode low-noise ultrasonic skip mode typical operating characteristics (circuit of figure 1, v in = 12v, v dd = v cc = 5v, ton = ref, t a = +25c, unless otherwise noted.)
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator ______________________________________________________________________________________ 11 standby and shutdown input supply current vs. input voltage MAX17101 toc10 input voltage (v) supply current (ma) 15 20 510 0.1 1 0.01 025 standby (onldo = v in ) shutdown (onldo = on1 = on2 = gnd) ldo and rtc power-up MAX17101 toc11 200 s/div a. input supply, 5v/div b. 5v ldo, 2v/div 0v 0v 0v 0v a 12v b 5v c 3.3v d 2.0v 12v c. 3.3v rtc, 2v/div d. 2.0v ref, 1v/div ldo and rtc power removal MAX17101 toc12 200 s/div a. input supply, 5v/div b. 5v ldo, 2v/div 5v 3.3v 2v a 12v b 5v c 3.3v d 2.0v 12v c. 3.3v rtc, 2v/div d. 2.0v ref, 1v/div typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v dd = v cc = 5v, ton = ref, t a = +25c, unless otherwise noted.) 5v ldo load transient MAX17101 toc13 4 s/div a. ldo output, 100mv/div 5v 0.1a 0a a b b. load current, 100ma/div 5v smps startup and shutdown MAX17101 toc14 200 s/div a. 5v ldo output, 0.2v/div b. 5v smps output, 2v/div c. on1, 5v/div 5v 5v 0v 0v a 5v b 5v c 5v startup waveforms (switching regulators) MAX17101 toc15 100 s/div a. on1, 2v/div b. 5v smps output, 2v/div 5v 5v 0a 0v 0v 0v a b 5v c d 5v c. pgood1, 5v/div d. inductor current, 5a/div
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 12 ______________________________________________________________________________________ 3.3v smps load transient MAX17101 toc18 40 s/div a. load current, 5a/div b. 3.3v smps output, 100mv/div c. inductor current, 5a/div 3.3v 0.5a 0a a b c 6.5a power removal (smps uvlo response) MAX17101 toc19 10ms/div a. input voltage, 5v/div b. 5v ldo output, 2v/div 5v 5v 5v a b c d 7v c. 5v smps, 2v/div d. pgood1, 5v/div shutdown waveforms (switching regulators) MAX17101 toc16 200 s/div a. on1, 5v/div b. 5v smps output, 2v/div 5v 5v 0a 0v 0v 0v a b c d 5v c. pgood1, 2v/div d. inductor current, 5a/div 5v smps load transient (pwm mode) MAX17101 toc17 40 s/div a. load current, 2a/div b. 5v smps output, 100mv/div c. inductor current, 2a/div 5v 0a 0a a b c 3.1a typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v dd = v cc = 5v, ton = ref, t a = +25c, unless otherwise noted.)
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator ______________________________________________________________________________________ 13 pin description pin name function 1 ref 2v reference-voltage output. bypass ref to agnd with a 0.1f or greater ceramic capacitor. the reference can source up to 50a for external loads. loading ref degrades output-voltage accuracy according to the ref load-regulation error (see the typical operating characteristics ). the reference shuts down when on1, on2, and onldo are all pulled low. 2 ton switching-frequency setting input. select the out1/out2 switching frequencies by connecting ton as follows for: high (v cc ) = 200khz/300khz open (ref) = 400khz/300khz gnd = 400khz/500khz 3 v cc analog supply voltage input. connect v cc to the system supply voltage with a series 50 resistor, and bypass to analog gr ound using a 1f or greater ceramic capacitor. 4 onldo enable input for ldo. drive onldo high to enable the linear regulator (ldo) output. drive onldo low to shut down the linear regulator output. 5 rtc 3.3v always-on linear regulator output for rtc power. bypass rtc with a 1f or greater ceramic capacitor to analog gr ound. rtc can source at least 5ma for external load support. rtc power-up is required for controller operation. 6 in power-input supply. in powers the linear regulators (rtc and ldo) and senses the input voltage for the quick-pwm on-time one-shot timers. the high-side mosfets on-time is inversely proportional to the input voltage. bypass in with a 0.1f or greater ceramic capacitor to pgnd close to the MAX17101. 7 ldo tracking linear regulator output. bypass ldo with a 4.7f or greater ceramic capacitor. ldo can source at least 100ma for external load support. ldo is powered from in and its regulation threshold is set by ldosel. for preset 5v operation, connect ldosel directly to gnd. for preset 3.3v operation, connect ldosel directly to v cc . when ldo is used for 5v operation, ldo must supply v cc and v dd . 8 ldosel input for the linear regulator output voltage selection. ldosel sets the ldo regulation voltage. connect ldosel to gnd for a fixed 5v linear-regulator output voltage, or connect ldosel to v cc for a fixed 3.3v linear-regulator output voltage. 9 byp linear regulator bypass input. when byp voltage exceeds 93.5% of the ldo voltage, the controller bypasses the ldo output to the byp input. the bypass switch is disabled if the ldo voltage drops by 8.5% from its nominal regulation threshold. when not being used, connect byp to gnd. 10 out1 output voltage-sense input for smps1. out1 is an input to the quick-pwm on-time one-shot timer. out1 also serves as the feedback input for the preset 5v (fb1 = gnd) and 1.5v (fb1 = v cc ) output voltage settings. 11 fb1 adjustable feedback voltage-sense connection for smps1. connect fb1 to gnd for fixed 5v operation. connect fb1 to v cc for fixed 1.5v operation. connect fb1 to an external resistive voltage-divider from out1 to analog gr ound to adjust the output voltage between 0.7v and 5.5v. 12 ilim1 valley current-limit adjustment for smps1. the gnd - lx1 current-limit threshold is 1/10 the voltage present on ilim1 over a 0.2v to 2v range. an internal 5a current source allows this voltage to be set with a single resistor between ilim1 and analog ground. 13 pgood1 open-drain power-good output for smps1. pgood1 is low when the output voltage is more than 16% (typ) below the nominal regulation threshold, during soft-start, in shutdown, and after the fault latch has been tripped. after the soft-start circuit has terminated, pgood1 b ecomes high impedance if the output is in regulation.
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 14 ______________________________________________________________________________________ pin description (continued) pin name function 14 on1 enable input for smps1. drive on1 high to enable smps1. drive on1 low to shut down smps1. 15 dh1 high-side gate-driver output for smps1. dh1 swings from lx1 to bst1. 16 lx1 inductor connection for smps1. connect lx1 to the switched side of the inductor. lx1 is the lower supply rail for the dh1 high-side gate driver. 17 bst1 boost flying-capacitor connection for smps1. connect to an external capacitor as shown in figure 1. an optional resistor in series with bst1 allows the dh1 turn-on current to be adjusted. 18 dl1 low-side gate-driver output for smps1. dl1 swings from pgnd to v dd. 19 v dd supply-voltage input for the dl_ gate drivers. connect to a 5v supply. also connect to the drain of the bst diode switch. 20 secfb secondary feedback input. the s econdary feedback input forces the smps1 output into ultrasonic mode when the secfb voltage drops below its 2v threshold voltage. this forces dl1 and dh1 to switch, allowing the system to refresh an external low-power charge pump being driven by dl1 (see figure 1 for the standard application circuitmain supply ). connect secfb to v cc (the 5v bias supply) to disable secondary feedback. 21 agnd analog ground. connect backside exposed pad to agnd. 22 pgnd power ground 23 dl2 low-side gate-driver output for smps2. dl2 swings from pgnd to v dd. 24 bst2 boost flying-capacitor connection for smps2. connect to an external capacitor as shown in figure 1. an optional resistor in series with bst2 allows the dh2 turn-on current to be adjusted. 25 lx2 inductor connection for smps2. connect lx2 to the switched side of the inductor. lx2 is the lower supply rail for the dh2 high-side gate driver. 26 dh2 high-side gate-driver output for smps2. dh2 swings from lx2 to bst2. 27 on2 enable input for smps2. drive on2 high to enable smps2. drive on2 low to shut down smps2. 28 pgood2 open-drain power-good output for smps2. pgood2 is low when the output voltage is more than 150mv (typ) below the refin2 voltage or more than 16% below the preset voltage, during soft-start, in shutdown, and when the fault latch has been tripped. after the soft-start circuit has terminated, pgood2 becomes high impedance if the output is in regulation. pgood2 is blankedforced high-impedance statewhen a dynamic refin transition is detected. 29 skip pulse-skipping control input. this three-level input determines the operating mode for the switching regulators: high (v cc ) = forced-pwm operation open/ref (2v) = ultrasonic mode gnd = pulse-skipping mode 30 out2 output voltage-sense input for smps2. out2 is an input to the quick-pwm on-time one-shot timer. out2 also serves as the feedback input for the preset 3.3v (refin2 = v cc ) and 1.05v (refin2 = rtc). 31 ilim2 valley current-limit adjustment for smps2. the gnd - lx2 current-limit threshold is 1/10 the voltage present on ilim2 over a 0.2v to 2v range. an internal 5a current source allows this voltage to be set with a single resistor between ilim2 and analog ground. 32 refin2 external reference input for smps2. refin2 sets the feedback-regulation voltage (v out2 = v refin2 ). connect refin2 to rtc for fixed 1.05v operation. connect refin2 to v cc for fixed 3.3v operation. ep exposed pad. connect the backside exposed pad to agnd.
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator ______________________________________________________________________________________ 15 figure 1. standard application circuitmain supply ldo dh2 bst2 5v ldo output input (v in )* 7v to 24v 5v output dl2 lx2 pgnd agnd rgnd 0 power-good } pgood1 n l1 n l2 n h1 n h2 c bst1 0.1 f c bst2 0.1 f dh1 bst1 dl1 lx1 on1 on2 off on pgood2 r7 100k r6 100k l1 c out1 c out2 ilim1 out1 fb1 l2 ilim2 out2 refin2 onldo in rtc v dd v cc pad 3.3v output 12v to 15v charge pump secfb byp c3 1 f ldosel ref c4 0.1 f ton x out1/out2 switching frequency open (ref): 400khz/300khz c2 1.0 f r4 500k r5 100k r1 47 c1 4.7 f c5 10nf c6 0.1 f 5v smps output (out1) c8 0.1 f r ilim1 r ilim2 d2 c in 4 x 10 f 25v c22 0.1 f d x1 d x2 rtc supply d1 skip power ground analog ground MAX17101 c7 10nf *lower input voltages require additional input capacitance. if operating near dropout, component selection must be carefully done to ensure proper operation. place c22 between in and pgnd as close to the MAX17101 as possible.
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 16 ______________________________________________________________________________________ figure 2. functional diagram overview fb1 2v ref dh2 bst2 lx2 v dd dl2 dh1 bst1 lx1 v dd dl1 pwm1 controller (figure 3) pgnd fb select (preset vs. adj) on1 refin2 on2 ilim2 out2 ton ilim1 out1 power-good and fault protection fault1 skip 5v linear regulator ldo gnd ldo bypass circuitry onldo pgood1 pgood2 v dd uvlo uvlo fault2 3.3v linear regulator rtc pad ref v dd in byp ldosel secfb v cc MAX17101 pwm2 controller (figure 3) fb select (preset vs. adj) power-good and fault protection
MAX17101 component 400khz/300khz smps 1: 5v at 5a smps 2: 3.3v at 8a 400khz/500khz smps 1: 5v at 3a smps 2: 3.3v at 5a 400khz/300khz smps 1: 1.5v at 8a smps 2: 1.05v at 5a input voltage v in = 7v to 24v v in = 7v to 24v v in = 7v to 24v input capacitor (c in ) (4x) 10f, 25v taiyo yuden (2x) 10f, 25v taiyo yuden (4x) 10f, 25v taiyo yuden smps 1 output capacitor (c out1 ) 330f, 6v, 18m sanyo 6tpe330mil 330f, 6v, 18m sanyo 6tpe330mil (2x) 330f, 2v, 7m sanyo 2tpf330m7 inductor (l1) 4.3h, 11.4m , 11a sumida cep125u 4.7h, 9.8m , 7a sumida cdrh10d68 1.5h, 12a, 7m nec/tokin mplc1040l1r5 high-side mosfet (n h1 ) fairchild semiconductor fds6612a 26m /30m , 30v fairchild semiconductor fds8690 8.6m /11.4m , 30v low-side mosfet (n l1 ) fairchild semiconductor fds6670s 9m /11.5m , 30v vishay siliconix si4814dy dual 30v mosfet high side: 19m /23m low side: 18m /22m fairchild semiconductor fdms8660s 2.6m /3.5m , 30v current-limit resistor (r ilim1 ) 200k 150k 49.9k smps 2 output capacitor (c out2 ) 470f, 4v, 15m sanyo 4tpe470mfl 330f, 6v, 18m sanyo 6tpe330mil 330f, 2v, 7m sanyo 2tpf330m7 inductor (l2) 4.3h, 11.4m , 11a sumida cep125u 4.7h, 9.8m , 7a sumida cdrh10d68 1.5h, 12a, 7m nec/tokin mplc1040l1r5 high-side mosfet (n h2 ) fairchild semiconductor fds8690 8.6m /11.4m , 30v fairchild semiconductor fds8690 8.6m /11.4m , 30v low-side mosfet (n l2 ) fairchild semiconductor fdms8660s 2.6m /3.5m , 30v vishay siliconix si4814dy dual 30v mosfet high side: 19m /23m low side: 18m /22m fairchild semiconductor fdms8660s 2.6m /3.5m , 30v current-limit resistor (r ilim2 ) 200k 200k 49.9k table 1. component selection for standard applications supplier website renesas technology corp. www.renesas.com sanyo electric co., ltd. www.sanyodevice.com sumida corp. www.sumida.com taiyo yuden www.t-yuden.com tdk corp. www.component.tdk.com toko america, inc. www.tokoam.com vishay (dale, siliconix) www.vishay.com wrth elektronik gmbh & co. kg www.we-online.com supplier website avx corporation www.avxcorp.com central semiconductor www.centralsemi.com fairchild semiconductor www.fairchildsemi.com international rectifier www.irf.com kemet corp. www.kemet.com nec/tokin corp. www.nec-tokinamerica.com panasonic corp. www.panasonic.com philips/nxp www.semiconductors.philips.com pulse engineering www.pulseeng.com table 2. component suppliers dual quick-pwm, step-down controller with low-power ldo, rtc regulator ______________________________________________________________________________________ 17
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 18 ______________________________________________________________________________________ detailed description the MAX17101 step-down controller is ideal for high- voltage, low-power supplies for notebook computers. maxims quick-pwm pulse-width modulator in the MAX17101 is specifically designed for handling fast load steps while maintaining a relatively constant oper- ating frequency and inductor operating point over a wide range of input voltages. the quick-pwm architec- ture circumvents the poor load-transient timing prob- lems of fixed-frequency current-mode pwms, while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant-off-time pwm schemes. figure 2 is a functional diagram overview. figure 3 is the functional diagramquickpwm core. the MAX17101 includes several features for multipur- pose notebook functionality, allowing this controller to be used two or three times in a single notebookmain, i/o chipset, and graphics. the MAX17101 includes a 100ma ldo that can be configured for preset 5v oper- ationideal for initial power-up of the notebook and main supply. additionally, the MAX17101 includes a 3.3v, 5ma rtc supply that remains always enabled, which can be used to power the rtc supply and sys- tem pullups when the notebook shuts down. the MAX17101 also includes an optional secondary feed- back input that allows an unregulated charge pump or secondary winding to be included on a supplyideal for generating the low-power 12v-to-15v load switch supply. finally, the MAX17101 includes a reference input on smps 2 that allows dynamic voltage transitions when driven by an adjustable resistive voltage-divider or dacideal for the dynamic graphics core requirements. 3.3v rtc power the MAX17101 includes a low-current (5ma) linear reg- ulator that remains active as long as the input supply (in) exceeds 2v (typ). the main purpose of this always-enabled linear regulator is to power the real- time clock (rtc) when all other notebook regulators are disabled. rtc also serves as the main bias supply of the MAX17101 so it powers up before the ldc and switching regulators. the rtc regulator sources at least 5ma for external loads. adjustable 100ma linear regulator the MAX17101 includes a high-current (100ma) linear regulator that may be configured for preset 5v or 3.3v operation. when the MAX17101 is configured as a main supply, this ldo is required to generate the 5v bias supply necessary to power up the switching regulators. once the switching regulators are enabled, the ldo may be bypassed using the dedicated byp input. the adjustable linear regulator allows generation of the 3.3v suspend supply or buffered low-power chipset and gpu reference supplies. the MAX17101 ldo sources at least 100ma of supply current. bypass switch the MAX17101 includes an independent ldo bypass input that allows the ldo to be bypassed by either switching regulator output or from a different regulator all together. when the bypass voltage (byp) exceeds 93.5% of the ldo output voltage for 500s, the MAX17101 reduces the ldo regulation threshold and turns on an internal p-channel mosfet to short byp to ldo. instead of disabling the ldo when the MAX17101 enables the bypass switch, the controller reduces the ldo regulation voltage, which effectively places the linear regulator in a standby state while switched over, yet allows a fast recovery if the bypass supply drops. connect byp to gnd when not used to avoid uninten- tional conduction through the body diode (byp to ldo) of the p-channel mosfet. 5v bias supply (v cc /v dd ) the MAX17101 requires an external 5v bias supply (v dd and v cc ) in addition to the battery. typically, this 5v bias supply is generated by either the internal 100ma ldo (when configured for a main supply) or from the notebooks 95%-efficient 5v main supply (when configured for i/o chipset, ddr, or graphics). keeping these bias supply inputs independent improves the overall efficiency and allows the internal linear regulator to be used for other applications as well. the v dd bias supply input powers the internal gate dri- vers and the v cc bias supply input powers the analog control blocks. the maximum current required is domi- nated by the switching losses of the drivers and may be estimated as follows: i bias(max) = i cc(max) + f sw q g 30ma to 60ma (typ)
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator ______________________________________________________________________________________ 19 free-running constant-on-time pwm controller with input feed-forward the quick-pwm control architecture is a pseudo-fixed- frequency, constant on-time, current-mode regulator with voltage feed-forward. this architecture relies on the output filter capacitors esr to act as a current- sense resistor, so the feedback ripple voltage provides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose pulse width is inversely proportional to input voltage and directly proportional to output volt- age. another one-shot sets a minimum off-time (300ns typ). the on-time one-shot is triggered if the error com- parator is low, the low-side switch current is below the valley current-limit threshold, and the minimum off-time one-shot has timed out. on-time one-shot the heart of the pwm core is the one-shot that sets the high-side switch on-time. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. the high-side switch on-time is inversely proportional to the battery voltage as sensed by the in input, and proportional to the output voltage: on-time = k (v out /v in ) where k (switching period) is set by the trilevel ton input (see the pin description section). high-frequency (400khz/500khz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. this might be accept- able in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. low-frequency (200khz/300khz) oper- ation offers the best overall efficiency at the expense of component size and board space. for continuous conduction operation, the actual switching frequency can be estimated by: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pcb resistances; v drop2 is the sum of the resistances in the charging path, including the high-side switch, inductor, and pcb resistances; and t on is the on-time calculated by the MAX17101. f vv tvv sw out drop on in drop = + + 1 2 () switching regulator ton setting (khz) typical k-factor (s) k-factor error (%) comments 200 ton = v cc 5.0 10 use for absolute best efficiency. smps 1 400 ton = ref or gnd 2.5 12.5 useful in 3-cell systems for lighter loads than the cpu core or where size is key. 300 ton = ref or v cc 3.3 10 considered mainstream by current standards. smps 2 500 ton = gnd 2.0 12.5 good operating point for compound buck designs or desktop circuits. table 3. approximate k-factor errors
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 20 ______________________________________________________________________________________ figure 3. functional diagramquick-pwm core skip s r q s r* q dh driver dl driver slope compensation analog soft- start/stop valley current limit fb refin lx agnd gnd agnd on neg current limit zero crossing int preset or ext adj three-level decode ref gnd integrator *reset dominate 1-shot trig q t off(min) 1-shot trig q t on on-time compute ton in ilim vcc 1-shot trig q ultrasonic gnd fb refin ultrasonic threshold
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator ______________________________________________________________________________________ 21 modes of operation forced-pwm mode ( s s k k i i p p = v cc ) the low-noise forced-pwm mode ( skip = v cc ) dis- ables the zero-crossing comparator, which controls the low-side switch on-time. this forces the low-side gate- drive waveform to constantly be the complement of the high-side gate-drive waveform, so the inductor current reverses at light loads while dh maintains a duty factor of v out /v in . the benefit of forced-pwm mode is to keep the switching frequency fairly constant. however, forced-pwm operation comes at a cost: the no-load 5v bias current remains between 20ma to 60ma depend- ing on the switching frequency and mosfet selection. the MAX17101 automatically uses forced-pwm opera- tion during all transitionsstartup and shutdown regardless of the skip configuration. automatic pulse-skipping mode ( s s k k i i p p = gnd) in skip mode ( skip = gnd), an inherent automatic switchover to pfm takes place at light loads. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor currents zero crossing. the zero-crossing comparator threshold is set by the differential across lx and agnd. dc output-accuracy specifications refer to the integrat- ed threshold of the error comparator. when the induc- tor is in continuous conduction, the MAX17101 regulates the valley of the output ripple and the internal integrator removes the actual dc output-voltage error caused by the output-ripple voltage and internal slope compensation. in discontinuous conduction ( skip = gnd and i out < i load(skip) ), the integrator cannot correct for the low-frequency output ripple error, so the output voltage has a dc regulation level higher than the error comparator threshold by approximately 1.5% due to slope compensation and output ripple voltage. ultrasonic mode ( s s k k i i p p = open or ref) leaving skip unconnected or connecting skip to ref (2v) activates a unique pulse-skipping mode with a guaranteed minimum switching frequency of 20khz. this ultrasonic pulse-skipping mode eliminates audio- frequency modulation that would otherwise be present when a lightly loaded controller automatically skips pulses. in ultrasonic mode, the controller automatically transitions to fixed-frequency pwm operation when the load reaches the same critical conduction point (i load(skip) ) that occurs when normally pulse skipping. an ultrasonic pulse occurs (figure 4) when the con- troller detects that no switching has occurred within the last 37s or when secfb drops below its feedback threshold. once triggered, the ultrasonic circuitry pulls dl high, turning on the low-side mosfet to induce a negative inductor current. after the inductor current reaches the negative ultrasonic current threshold, the controller turns off the low-side mofet (dl pulled low) and triggers a constant on-time (dh driven high). when the on-time has expired, the controller reenables the low-side mosfet until the inductor current drops below the zero-crossing threshold. starting with a dl pulse greatly reduces the peak output voltage when compared to starting with a dh pulse. the output voltage at the beginning of the ultrasonic pulse determines the negative ultrasonic current threshold, resulting in the following equation: v neg(us) = i l r cs = (v nom - v fb ) x 0.385v where v nom is the nominal feedback-regulation volt- age, and v fb is the actual feedback voltage (v fb > v nom ), and r cs is the current-sense resistance seen across lx to agnd. secondary feedback: secfb?ut1 only when the controller skips pulses ( skip = gnd or ref), the long time between pulses (especially if the output is sinking current) allows the external charge-pump voltage or transformer secondary winding voltage to drop. when the secfb voltage drops below its 2v feedback thresh- old, the MAX17101 issues an ultrasonic pulse (regardless of the ultrasonic one-shot state). this forces a switching cycle, allowing the external unregulated charge pump (or transformer secondary winding) to be refreshed. see the ultrasonic mode ( skip = open or ref) section for switching cycle sequence/specifications. on-time (t on ) i sonic zero-crossing detection 0 37 s (typ) inductor current figure 4. ultrasonic waveforms
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 22 ______________________________________________________________________________________ automatic fault blanking when the MAX17101 automatically detects that the internal target and refin2 are more than 25mv (typ) apart, the controller automatically blanks pgood2, blanks the uvp protection, and sets the ovp threshold to ref + 200mv. the blanking remains until 1) the internal target and refin2 are within 20mv of each other and 2) an edge is detected on the error amplifier signifying that the output is in regulation. this prevents the system or internal fault protection from shutting down the controller during transitions. valley current-limit protection the current-limit circuit employs a unique valley cur- rent-sensing algorithm that senses the inductor current through the low-side mosfetacross lx to agnd. if the current through the low-side mosfet exceeds the valley current-limit threshold, the pwm controller is not allowed to initiate a new cycle. the actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the inductor value and bat- tery voltage. when combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. in forced-pwm mode, the MAX17101 also implements a negative current limit to prevent excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold is set to approximately 120% of the positive current limit. por, uvlo when v cc rises above the power-on reset (por) thresh- old, the MAX17101 clears the fault latches, forces the low-side mosfet to turn on (dl high), and resets the soft-start circuit, preparing the controller for power-up. however, the v cc undervoltage lockout (uvlo) circuitry inhibits switching until v cc reaches 4.2v (typ). when v cc rises above 4.2v and the controller has been enabled (on_ pulled high), the controller activates the enabled pwm controllers and initializes soft-start. when v cc drops below the uvlo threshold (falling edge), the controller stops switching, and dh and dl are pulled low and a 10 switch discharges the outputs. when the 2v por falling-edge threshold is reached, the dl state no longer matters since there is not enough volt- age to force the switching mosfets into a low on-resis- tance state, so the controller pulls dl high, allowing a soft discharge of the output capacitors (damped response). however, if the v cc recovers before reaching the falling por threshold, dl remains low until the error comparator has been properly powered up and triggers an on-time. only one enable input needs to be toggled to clear the fault latches and activate both outputs. soft-start and soft-shutdown the MAX17101 includes voltage soft-start and soft- shutdownslowly ramping up and down the target voltage. during startup, the slew-rate control softly slews the preset/fixed target voltage over a 1ms startup period or its tracking voltage (refin2 < 2v) with a 1mv/s slew rate. this long startup period reduces the inrush current during startup. when on1 or on2 is pulled low or the output undervolt- age fault latch is set, the respective output automatically enters soft-shutdownthe regulator enters pwm mode and ramps down its preset/fixed output voltage over a 1ms period or its tracking voltage (refin2 < 2v) with a 1mv/s slew rate. after the output voltage drops below 0.1v, the MAX17101 pulls dl high, clamping the output and lx switching node to ground, preventing leakage currents from pulling up the output and minimizing the negative output-voltage undershoot during shutdown. output voltage dc output-accuracy specifications in the electrical characteristics table refer to the error comparators threshold. when the inductor continuously conducts, the MAX17101 regulates the valley of the output ripple, so the actual dc output voltage is lower than the slope-com- pensated trip level by 50% of the output ripple voltage. for pwm operation (continuous conduction), the output voltage is accurately defined by the following equation: where v nom is the nominal feedback voltage, a ccv is the integrators gain, and v ripple is the output ripple voltage (v ripple = esr x i inductor , as described in the output capacitor selection section). in discontinuous conduction (i out < i load(skip) ), the longer off-times allow the slope compensation to increase the threshold voltage by as much as 1%, so the output voltage regulates slightly higher than it would in pwm operation. internal integrator the internal integrator improves the output accuracy by removing any output accuracy errors caused by the slope compensation, output ripple voltage, and error- amplifier offset. therefore, the dc accuracy (in forced- pwm mode) depends on the integrators gain, the inte- grators offset, and the accuracy of the integrators refe- rence input. vv v a out pwm nom ripple ccv () =+ ? ? ? ? ? ? 2
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator ______________________________________________________________________________________ 23 adjustable/fixed output voltages connect fb1 to gnd for fixed 5v operation. connect fb1 to v cc for fixed 1.5v operation. connect fb1 to an exter- nal resistive voltage-divider from out1 to analog ground to adjust the output voltage between 0.7v and 5.5v. during soft-shutdown, application circuits configured for adjustable feedback briefly switch modes when fb1 drops below the 110mv dual-mode threshold. choose r fbl (resistance from fb1 to agnd) to be approximately 49.9k and solve for r fbh (resistance from out1 to fb1) using the following equation: connect refin2 to v cc for fixed 3.3v operation. connect refin2 to rtc (3.3v) for fixed 1.05v operation. connect refin2 to an external resistive voltage-divider from ref to analog ground to adjust the output voltage between 0.8v and 2v. choose r refinl (resistance from refin2 to gnd) to be approximately 49.9k and solve for r refinh (resis- tance from ref to refin2) using the equation: power-good outputs (pgood) and fault protection pgood is the open-drain output that continuously monitors the output voltage for undervoltage and over- voltage conditions. pgood_ is actively held low in shutdown (on_ = gnd), during soft-start or soft-shut- down. approximately 20s (typ) after the soft-start terminates, pgood_ becomes high impedance as long as the feedback voltage exceeds 85% of the nominal fixed-regulation voltage or within 150mv of the refin2 input voltage. pgood_ goes low if the feedback volt- age drops 16% below the fixed target voltage, or if the output voltage drops 150mv below the dynamic refin2 voltage, or if the smps controller is shut down. for a logic-level pgood_ output voltage, connect an external pullup resistor between pgood_ and v dd . a 100k pullup resistor works well in most applications. overvoltage protection (ovp) when the output voltage rises 16% above the regula- tion voltage, the controller immediately pulls the respective pgood_ low, sets the overvoltage fault latch, and immediately pulls the respective dl_ high clamping the output to gnd. toggle either on1 or on2 input, or cycle v cc power below its por threshold to clear the fault latch and restart the controller. undervoltage protection (uvp) when the output voltage drops 30% below the regula- tion voltage, the controller immediately pulls the respec- tive pgood_ low, sets the undervoltage fault latch, and begins the shutdown sequence. after the output volt- age drops below 0.1v, the synchronous rectifier turns on, clamping the output to gnd. toggle either on1 or on2 input, or cycle v cc power below its por threshold to clear the fault latch and restart the controller. thermal-fault protection (t shdn ) the MAX17101 features a thermal-fault protection circuit. when the junction temperature rises above +160c, a thermal sensor activates the fault latch, pulls pgood1 and pgood2 low, enables the 10 discharge circuit, and disables the controllerdh and dl pulled low. toggle onldo or cycle in power to reactivate the con- troller after the junction temperature cools by 15c. rr v v refinh refinl ref out =? ? ? ? ? ? ? 2 1 rr v v fbh fbl out =? ? ? ? ? ? ? 1 07 1 . mode controller state driver state shutdown (on_ = high to low); output uvp (latched) voltage soft-shutdown initiated. internal error-amplifier target slowly ramped down to gnd and output actively discharged (automatically enters forced-pwm mode). dl driven high and dh pulled low after soft-shutdown completed (output < 0.1v). output ovp (latched) controller shuts down and ea target internally slewed down. controller remains off until on_ toggled or v cc power cycled. dl immediately driven high, dh pulled low. v cc uvlo falling-edge thermal fault (latched) smps controller disabled (assuming on_ pulled high), 10 output discharge active. dl and dh pulled low. v cc uvlo rising edge smps controller enabled (assuming on_ pulled high). dl driven high, dh pulled low. v cc por smps inactive, 10 output discharge active. dl driven high, dh pulled low. table 4. fault protection and shutdown operation table
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 24 ______________________________________________________________________________________ design procedure firmly establish the input-voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switching fre- quency and inductor operating point, and the following four factors dictate the rest of the design: ? input voltage range: the maximum value (v in(max) ) must accommodate the worst-case, high ac-adapter voltage. the minimum value (v in(min) ) must account for the lowest battery voltage after drops due to connectors, fuses, and battery-selector switches. if there is a choice at all, lower input volt- ages result in better efficiency. ? maximum load current: there are two values to consider. the peak load current (i load(max) ) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the conti- nuous load current (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat- contributing components. ? switching frequency: this choice determines the basic trade-off between size and efficiency. the opti- mal frequency is largely a function of maximum input voltage due to mosfet switching losses that are proportional to frequency and v in 2 . the optimum fre- quency is also a moving target due to rapid improve- ments in mosfet technology that are making higher frequencies more practical. ? inductor operating point: this choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. low inductor values provide better transient response and smaller phy- sical size, but also result in lower efficiency and higher output ripple due to increased ripple cur- rents. the minimum practical inductor value is one that causes the circuit to operate at the edge of cri- tical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size- reduction benefit. the optimum operating point is usually found between 20% and 50% ripple current. when pulse skipping ( skip low and light loads), the inductor value also determines the load-current value at which pfm/pwm switchover occurs. inductor selection the switching frequency and inductor operating point determine the inductor value as follows: for example: i load(max) = 4a, v in = 12v, v out2 = 2.5v, f sw = 355khz, 30% ripple current or lir = 0.3: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): most inductor manufacturers provide inductors in stan- dard values, such as 1.0h, 1.5h, 2.2h, 3.3h, etc. also look for nonstandard values, which can provide a better compromise in lir across the input voltage range. if using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the lir with properly scaled inductance values. transient response the inductor ripple current also impacts transient- response performance, especially at low v in - v out dif- ferentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the amount of output sag is also a function of the maxi- mum duty factor, which can be calculated from the on- time and minimum off-time: where t off(min) is the minimum off-time (see the electrical characteristics ) and k is from table 3. the amount of overshoot during a full-load to no-load tran- sient due to stored inductor energy can be calculated as: v il cv soar load max out out () () 2 2 v li vk v t sag load max out in off min = () ? ? ? ? ? ? + () ( 2 ) ) ( ? ? ? ? ? ? ? () ? ? ? ? ? ? ? 2c v vv k v t out out in out in off m min) ? ? ? ? ii lir peak load max =+ ? ? ? ? ? ? () 1 2 l vvv vkhza h = ? = 25 12 25 12 355 4 0 3 465 .( .) . . l vvv v f i lir ripple in out in sw load max = ? () ()
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator ______________________________________________________________________________________ 25 setting the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half the ripple current; therefore: where i lim(val) equals the minimum valley current-limit threshold voltage divided by the current-sense resis- tance (r sense ). when using a 100k ilim resistor, the minimum valley current-limit threshold is 40mv. connect a resistor between ilim_ and analog ground (agnd) to set the adjustable current-limit threshold. the valley current-limit threshold is approximately 1/10 the ilim voltage formed by the external resistance and internal 5a current source. the 40k to 400k adjust- ment range corresponds to a 20mv to 200mv valley cur- rent-limit threshold. when adjusting the current limit, use 1% tolerance resistors to prevent significant inaccuracy in the valley current-limit tolerance. output capacitor selection the output filter capacitor must have low enough equiv- alent series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. for processor core voltage converters and other appli- cations where the output is subject to violent load tran- sients, the output capacitors size depends on how much esr is needed to prevent the output from dip- ping too low under a load transient. ignoring the sag due to finite capacitance: in applications without large and fast load transients, the output capacitors size often depends on how much esr is needed to maintain an acceptable level of out- put voltage ripple. the output ripple voltage of a step- down controller equals the total inductor ripple current multiplied by the output capacitors esr. therefore, the maximum esr required to meet ripple specifications is: the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tanta- lums, os-cons, polymers, and other electrolytics). when using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent v s ag and v s oar from causing problems during load transients. generally, once enough capacitance is added to meet the over- shoot requirement, undershoot at the rising load edge is no longer a problem (see the v s ag and v s oar equa- tions in the transient response section). however, low- capacity filter capacitors typically have high esr zeros that may affect the overall stability (see the output capacitor stability considerations section). output capacitor stability considerations for quick-pwm controllers, stability is determined by the value of the esr zero relative to the switching fre- quency. the boundary of instability is given by the fol- lowing equation: where: for a typical 300khz application, the esr zero frequen- cy must be well below 95khz, preferably below 50khz. tantalum and os-con capacitors in widespread use at the time of publication have typical esr zero fre- quencies of 25khz. in the design example used for inductor selection, the esr needed to support 25mv p-p ripple is 25mv/1.2a = 20.8m . one 220f/4v sanyo polymer (tpe) capacitor provides 15m (max) esr. this results in a zero at 48khz, well within the bounds of stability. do not put high-value ceramic capacitors directly across the feedback sense point without taking precau- tions to ensure stability. large ceramic capacitors can have a high-esr zero frequency and cause erratic, unstable operation. however, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. f rc esr esr out = 1 2 f f esr sw r v i lir esr ripple load max () r v i esr step load max () ii ilir lim val load max load max () ( ) () >? ? ? ? ? ? ? 2
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 26 ______________________________________________________________________________________ unstable operation manifests itself in two related but distinctly different ways: double-pulsing and fast-feed- back loop instability. double-pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this fools the error comparator into triggering a new cycle immediately after the 400ns minimum off- time period has expired. double-pulsing is more annoy- ing than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability results in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents: for most applications, nontantalum chemistries (ceramic, aluminum, or os-con) are preferred due to their resis- tance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. if the MAX17101 is operated as the second stage of a two-stage power conversion system, tantalum input capacitors are acceptable. in either configuration, choose a capacitor that has less than 10c tempera- ture rise at the rms input current for optimal reliability and lifetime. power-mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20v) ac adapters. low-current applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . ideally, the losses at v in(min) should be roughly equal to the losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher, consider increasing the size of n h . conversely, if the losses at v in(max) are significantly higher, consider reducing the size of n h . if v in does not vary over a wide range, maximum efficiency is achieved by selecting a high-side mosfet (n h ) that has conduction losses equal to the switching losses. choose a low-side mosfet (n l ) that has the lowest possible on-resistance (r ds(on) ), comes in a moder- ate-sized package (i.e., 8-pin so, dpak, or d 2 pak), and is reasonably priced. ensure that the MAX17101 dl_ gate driver can supply sufficient current to support the gate charge and the current injected into the para- sitic drain-to-gate capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction prob- lems can occur. switching losses are not an issue for the low-side mosfet since it is a zero-voltage switched device when used in the step-down topology. power-mosfet dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at minimum input voltage: generally, use a small high-side mosfet to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissi- pation often limits how small the mosfet can be. the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high-side switching loss- es do not become an issue until the input is greater than approximately 15v. calculating the power dissipation in high-side mosfets (n h ) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influ- ence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pcb layout characteristics. the following switching loss calculation provides only a very rough estimate and is no substi- tute for breadboard evaluation, preferably including verification using a thermocouple mounted on n h : pd n switching vifq i vc f h max load sw g sw gate in oss sw ( ) () () = ? ? ? ? ? ? + ? ? ? ? ? ? 2 2 pd n sistive v v ir h out in load ds o (re ) ( = ? ? ? ? ? ? () 2 n n) ii vvv v rms load out in out in = ? ? ? ? ? ? ? ()
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator ______________________________________________________________________________________ 27 where c oss is the high-side mosfets output capaci- tance, q g(sw) is the charge needed to turn on the high-side mosfet, and i gate is the peak gate-drive source/sink current (1a typ). switching losses in the high-side mosfet can become a heat problem when maximum ac adapter voltages are applied due to the squared term in the switching- loss equation provided above. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when subjected to v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum battery voltage: the absolute worst case for mosfet power dissipation occurs under heavy overload conditions that are greater than i load(max) , but are not high enough to exceed the current limit and cause the fault latch to trip. to protect against this possibility, overdesign the cir- cuit to tolerate: where i valley(max) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and sense-resistance variation. the mosfets must have a relatively large heatsink to han- dle the overload power dissipation. choose a schottky diode (d l ) with a forward voltage drop low enough to prevent the low-side mosfets body diode from turning on during the dead time. as a general rule, select a diode with a dc current rating equal to 1/3 the load current. this diode is optional and can be removed if efficiency is not critical. applications information step-down converter dropout performance the output-voltage adjustable range for continuous- conduction operation is restricted by the nonadjustable minimum off-time one-shot. for best dropout perfor- mance, use the slower (200khz) on-time setting. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. manufacturing tolerances and internal propa- gation delays introduce an error to the ton k-factor. this error is greater at higher frequencies (table 3). also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the v s ag equation in the transient response section). the absolute point of dropout is when the inductor cur- rent ramps down during the minimum off-time ( i down ) as much as it ramps up during the on-time ( i up ). the ratio h = i up / i down indicates the controllers ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and v s ag greatly increases unless additional output capacitance is used. a reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between v s ag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: where v chg is the parasitic voltage drop in the charge path (see the on-time one-shot section), t off(min) is from the electrical characteristics , and k (1/f sw ) is taken from table 3. the absolute minimum input volt- age is calculated with h = 1. if the calculated v in(min) is greater than the required minimum input voltage, operating frequency must be reduced or output capacitance added to obtain an acceptable v s ag . if operation near dropout is antici- pated, calculate v s ag to be sure of adequate transient response. dropout design example: v out2 = 2.5v f sw = 355khz k = 3.0s, worst-case k min = 3.3s t off(min) = 500ns v chg = 100mv h = 1.5: v vv ns s in min () .. . . = + ? ? ? ? ? ? ? = 25 01 1 1 5 500 30 3. .47v v vv ht k in min out chg off min () () = + ? ? ? ? ? ? ? 1 ii i lir load valley max load max + ? ? ? ? ? ? () () 2 pd n sistive v v ir l out in max load ds on ( re ) () () =? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () 1 2
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 28 ______________________________________________________________________________________ calculating again with h = 1 and the typical k-factor value (k = 3.3s) gives the absolute limit of dropout: therefore, v in(min) must be greater than 3.06v, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.47v. pcb layout guidelines careful pcb layout is critical to achieving low switching losses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. follow these guidelines for good pcb layout: ? keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. ? keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pcbs (2oz vs. 1oz) can enhance full- load efficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. ? minimize current-sensing errors by connecting lx_ directly to the drain of the low-side mosfet. ? when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. ? route high-speed switching nodes (bst_, lx_, dh_, and dl_) away from sensitive analog areas (ref, fb_, and out_). a sample layout is available in the MAX17101 evalua- tion kit data sheet. layout procedure 1) place the power components first, with ground ter- minals adjacent (n l_ source, c in , c out_ , and d l_ anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet, preferably on the back side opposite n l_ and n h_ to keep lx_, gnd, dh_, and the dl_ gate- drive lines short and wide. the dl_ and dh_ gate traces must be short and wide (50 mils to 100 mils wide if the mosfet is 1in from the controller ic) to keep the driver impedance low and for proper adaptive dead-time sensing. 3) group the gate-drive components (bst_ capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figure 1. this diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go; and an analog ground plane for sensitive analog compo- nents. the analog ground plane and power ground plane must meet only at a single point directly at the ic. 5) connect the output power planes directly to the out- put filter capacitor positive and negative terminals with multiple vias. place the entire dc-dc converter circuit as close to the load as is practical. v vv ns s in min () .. . . = + ? ? ? ? ? ? ? = 25 01 1 1 500 33 306 6v MAX17101 max8778 rtc power-up required for controller operation. ldo and switching regulators independent of rtc operation. ldo does not support 0.3v ~ 2v adjustable output; ldo is preset to 5v or 3.3v. ldo external reference input for 0.3v ~ 2v adjustable output in addition to preset 5v or 3.3v. table 5. MAX17101 vs. max8778 design differences
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator ______________________________________________________________________________________ 29 figure 5. standard output application circuitchipset supply byp dh2 bst2 5v system supply input (v in )* 7v to 24v 1.5v output dl2 lx2 pgnd power-good } pgood1 n l1 n l2 n h1 n h2 c bst1 0.1 f c bst2 0.1 f dh1 bst1 dl1 lx1 on1 on2 off on pgood2 r7 100k r6 100k l1 c out1 c out2 ilim1 out1 fb1 l2 ilim2 out2 onldo in v dd v cc pad 1.05v output 3.3v smps supply secfb ton x out1/out2 switching frequency open (ref): 400khz/300khz c1 4.7 f c2 1.0 f 3.3 smps supply c5 1 f r ilim1 r ilim2 c in 2x 10 f 25v skip power ground analog ground MAX17101 ldo 3.3v ldo output c6 4.7 f c22 0.1 f refin2 r10 47 ldosel rtc c3 1 f ref c4 0.1 f rtc supply place c22 between in and pgnd as close to the MAX17101 as possible. agnd rgnd 0
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator 30 ______________________________________________________________________________________ package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 32 tqfn-ep t3255-3 21-0140 chip information process: bicmos
MAX17101 dual quick-pwm, step-down controller with low-power ldo, rtc regulator maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 31 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 8/08 initial release 1 2/09 minor edits. 1, 5, 14

▲Up To Search▲

Price & Availability of MAX17101

	To Download MAX17101 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .